1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a static random access memory (hereinafter, referred to simply as "SRAM") and a method of fabricating the same.
2. Description of the Related Art
Higher integration in a semiconductor device these days has made a device become smaller and smaller in size, and it has become quite difficult to have a sufficient margin to align a contact hole with a mask used for wiring arrangement. As a solution to this problem, there has been widely used the technique to form a contact hole in self-aligning fashion. Hereinbelow will be explained a conventional SRAM having a ground contact hole formed in self-aligning fashion.
FIG. 1 illustrates a SRAM cell having ground wiring arrangement. Gate electrodes 220 are formed on a field oxide film 202 and diffusion layers 206. A ground wiring 230 is formed above contact holes 210, and is connected to the diffusion layers 206 through the contact holes 210.
FIGS. 2A, 3A, 4A and 5A are cross-sectional views taken along the line A--A in FIG. 1, and FIGS. 2B, 3B, 4B and 5B are cross-sectional views taken along the line B--B in FIG. 1. FIGS. 2A to 5B illustrate respective steps of a method of fabricating the SRAM cell illustrated in FIG. 1. Hereinbelow is explained the method with reference to those drawings.
First, as illustrated in FIGS. 2A and 2B, a field oxide film 202 and a gate oxide film 203 are formed on a silicon substrate 201. Then, gate electrodes are formed on the silicon substrate 201 through the oxide films 202 and 203. Each of the gate electrodes has a two-layered structure including a polysilicon film 204 and an oxide film 205 lying on the polysilicon film 204.
Then, as illustrated in FIG. 3B, ion-implantation is carried out with the gate electrodes acting as a mask to thereby form n-type diffusion layers 206. Then, a resultant is entirely covered with an oxide film followed by anisotropic etching to thereby form insulating sidewall films 207 around sidewalls of the gate electrodes. Then, a resultant is entirely covered with an interlayer insulating film or an oxide film 208, as illustrated in FIGS. 3A and 3B.
Then, as illustrated in FIGS. 4A and 4B, a photoresist pattern is formed over a resultant, followed by anisotropic etching with the photoresist pattern acting as a mask to thereby form a contact hole 210 in self-aligning fashion about the polysilicon film 204.
Then, after the photoresist pattern 209 has been removed, a resultant is entirely covered with a tungsten silicide film 211 which will work as a ground wiring.
In the above mentioned conventional method of fabricating a semiconductor device, as indicated with an arrow C in FIG. 5A, the tungsten silicide film 211 cannot avoid to have poor coverage in an area where a spacing between the adjacent gate electrodes is quite small. As a result, the tungsten silicide film 211 has just a small thickness in such an area, and hence has a wiring resistance three to four times greater than that of an area having sufficient coverage, that is, a planarized area. This is accompanied with a problem that ON-state current of a driver transistor in SRAM is deteriorated to thereby cause an effective ratio to reduce with the result of deterioration in SRAM performance.
Even if the tungsten silicide film 211 is formed thicker, a thickness of the tungsten silicide film 211 is not increased so much in an area indicated with an arrow C where a spacing between the gate electrodes is quite small. Thus, the formation of the tungsten silicide film 211 thicker does not solve the above mentioned problem. In addition, the formation of the tungsten silicide film 211 thicker increases fabrication time. From this standpoint, the formation of the tungsten silicide film 211 thicker is not appropriate.
As illustrated in FIGS. 2B, 3B, 4B and 5B each showing a cross-section taken along the line B--B in FIG. 1, sufficient coverage is provided for an area where the oxide film 208 is formed over the gate electrodes and the contact hole 210 is formed in self-aligning fashion by making use of a step formed at the oxide film 205. On the other hand, the above mentioned problem of the poor coverage arises in such an area as illustrated in FIG. 5A where a contact hole is not formed. This problem is inherent to a highly integrated semiconductor device which forms a contact hole in self-aligning fashion.
To solve the above mentioned problem, it is considered that a ground wiring is made of material having superior coverage, such as polysilicon. However, composing a ground wiring of polysilicon brings a new problem that polysilicon would generate higher contact resistance and wiring resistance than those of tungsten silicide.